Codasip

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Codasip is an independant European company that designs customisable RISC-V semiconductor intellectual property (IP) and sells electronic design automation (EDA) software.[1] It is a founding member of RISC-V International.[2]

Now headquartered in Munich, the company has various design centres across Europe and has around 200 employees.[3]

History

Codasip was founded in 2014, by Karel Masařík – after 10 years of research.[4]

In 2015, the company co-founded RISC-V International[5] and released world's first RISC-V commercial IP core.

In 2019 it received funding support from the EU's "Horizon" Program.[6]

In 2022, it received support from the European Investment Bank[7] and was named as one of the start-ups to follow in EETimes "Silicon 100".[8]

Technology and products

Codasip has developed a tool, called Codasip Studio,[9] that enables the creation and modification of processor cores from a high-level description language called CodAL.[10] Codasip Studio is an EDA suite that comprises application profiling, processor model simulation, SDK generation, high-level synthesis, and verification environment generation. This is typical of an application-specific instruction set processor (ASIP) design tool.[11][12]

The company has also developed a range of RISC-V IP cores[13] that can be used in embedded and high-performance applications, including in multi-core applications.[14]

The fact that the Codasip IP are written in CodAL, the complementarity with the tools and the ability of the RISC-V standard to support custom instructions, enable fast exploration and customisation of the CPU.[15][16]

The customisable processors from Codasip have been recognised by the Embedded Computing Design industry award in 2022.[17]

References

  1. "CODASIP (IDGF)". www.eib.org. Retrieved 2023-07-31.
  2. "Members – RISC-V International". Retrieved 2023-07-31.
  3. "Start-up-Check: Chips zum Selbermachen mit den Bauplänen von Codasip". www.handelsblatt.com (in Deutsch). Retrieved 2023-07-31.
  4. Fassot, Frédéric (2020-10-21). "Architecture RISC-V : Codasip ouvre un centre de conception en France". VIPress.net (in français). Retrieved 2023-07-31.
  5. "History – RISC-V International". Retrieved 2023-07-31.
  6. "Codasip Awarded European Union Horizon 2020 Funding for Developing New RISC-V Processors". Design And Reuse. Retrieved 2023-07-31.
  7. "CODASIP (IDGF)". European Investment Bank. Retrieved 2023-07-31.
  8. Silicon 100: Startups to Follow in 2022. EETimes. 2022. pp. 84–86.
  9. "Codasip Studio". Codasip. Retrieved 2023-07-31.
  10. Arlot, Pierrick (16 April 2021). "Codasip offre la possibilité de s'exercer sur une implémentation réelle de processeur RISC-V". L'embarque (in français).
  11. Micconi, Laura; Gangadharan, Deepak; Pop, Paul; Madsen, Jan (June 2013). "Multi-ASIP platform synthesis for real-time applications". 2013 8th IEEE International Symposium on Industrial Embedded Systems (SIES). IEEE. pp. 59–67. doi:10.1109/SIES.2013.6601471. ISBN 978-1-4799-0658-1.
  12. Urquhart, Roddy (2021-04-22). "What Is An ASIP?". Semiconductor Engineering. Retrieved 2023-07-31.
  13. "Codasip RISC-V processors". Codasip. Retrieved 2023-07-31.
  14. Rousselot, Andre (2020-12-08). "Codasip lance 3 processeurs RISC‑V multicoeurs pour IA Edge". EENewsEurope (in français). Retrieved 2023-07-31.
  15. Fajcik, Martin; Smrz, Pavel; Zachariasova, Marcela (December 2017). "Automation of Processor Verification Using Recurrent Neural Networks". 2017 18th International Workshop on Microprocessor and SOC Test and Verification (MTV): 15–20. doi:10.1109/MTV.2017.15. ISBN 978-1-5386-3351-9.
  16. Elmohr, Mahmoud A.; Saleh, Mostafa A.; Eissa, Ahmed S.; Ahmed, Khaled E.; Farag, Mohammed M. (December 2016). "Hardware implementation of a SHA-3 application-specific instruction set processor". 2016 28th International Conference on Microelectronics (ICM). pp. 109–112. doi:10.1109/ICM.2016.7847921. ISBN 978-1-5090-5721-4.
  17. Media, OpenSystems. "Embedded World 2022 Best in Show Winners: Processors & IP". Embedded Computing Design. Retrieved 2023-07-31.

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